Best Jasper prompts for Computer Hardware Engineers

Design a PCIe switch architecture for a high-performance computing system with 16 endpoints, each requiring a minimum bandwidth of 10GB/s, and a maximum latency of 100ns. The switch must support up to 4 virtual functions per endpoint and have a minimum of 2x oversubscription. Provide a detailed block diagram, including the number of lanes, ports, and virtual channels, as well as a description of the arbitration and flow control mechanisms. Assume a x16 PCIe 4.0 interface and a 28nm CMOS process technology.

Analyze the system crash dump and logs to identify the root cause of a recurring system failure. The system consists of a quad-core processor, 16GB of DDR4 memory, and a custom-designed PCIe peripheral. The crash occurs randomly, but always during high-network-activity periods. Provide a step-by-step analysis of the crash dump, including the register values, memory dumps, and any relevant system logs. Identify the likely cause of the crash and recommend a course of action to debug and fix the issue.

Create a CAD model for a custom FPGA board with a Xilinx Virtex-7 XC7VX485T FPGA, 2GB of DDR3 memory, and a 10/100/1000 Ethernet interface. The board must fit within a 10x10cm form factor and have a maximum height of 2.5cm. Provide a detailed bill of materials, including the FPGA, memory, Ethernet controller, and any required passive components. Generate a 3D model of the board, including the PCB, FPGA, and any other components, and provide a description of the board's power delivery and thermal management systems.

Generate a deployment script for an embedded system consisting of a ARM Cortex-A9 processor, 1GB of DDR3 memory, and a custom-designed peripherals. The script must flash the FPGA with a bitstream, load the operating system and application software, and configure the system's network settings. Provide a detailed script, including the commands to program the FPGA, load the operating system, and configure the network settings. Assume a Linux-based operating system and a custom-designed FPGA bitstream.